1. Field of the Invention
Generally, the present disclosure relates to the formation of integrated circuits, and, more particularly, to the formation of metallization layers including highly conductive metals, such as copper, embedded into a dielectric material.
2. Description of the Related Art
In an integrated circuit, a very large number of circuit elements, such as transistors, capacitors, resistors and the like, are formed in or on an appropriate substrate, usually in a substantially planar configuration. Due to the large number of circuit elements and the required complex layout of advanced integrated circuits, the electrical connections of the individual circuit elements are generally not established within the same level on which the circuit elements are manufactured. Typically, such electrical connections are formed in one or more additional “wiring” layers, also referred to as metallization layers. These metallization layers generally include metal-containing lines, providing the intra-level electrical connection, and also include a plurality of inter-level connections, also referred to as vias, providing electrical connection between two neighboring stacked metallization layers, wherein the metal-containing lines and vias may also be commonly referred to as interconnect structures.
Due to the continuous shrinkage of the feature sizes of circuit elements in modern integrated circuits, the number of circuit elements for a given chip area, that is the packing density, also increases, thereby requiring an even larger increase in the number of electrical interconnections to provide the desired circuit functionality. Therefore, the number of stacked metallization layers may increase and the dimensions of the individual metal lines and vias may be reduced as the number of circuit elements per chip area becomes larger. The fabrication of a plurality of metallization layers entails extremely challenging issues to be solved, such as mechanical, thermal and electrical reliability of each metallization layer in the layer stack. As the complexity of integrated circuits advances and brings about the necessity for conductive lines that can withstand moderately high current densities, semiconductor manufacturers are increasingly replacing the well-known metallization metal aluminum with a metal that allows higher current densities and hence allows a reduction in the dimensions of the interconnections and thus the number of stacked metallization layers. For example, copper and alloys thereof are materials that are used to increasingly replace aluminum due to their superior characteristics in view of higher resistance against electromigration and significantly lower electrical resistivity when compared with aluminum. Despite these advantages, copper and copper alloys also exhibit a number of disadvantages regarding the processing and handling in a semiconductor facility. For instance, copper may not be efficiently applied onto a substrate in larger amounts by well-established deposition methods, such as chemical vapor deposition (CVD), and also may not be effectively patterned by the usually employed anisotropic etch procedures. Consequently, in manufacturing metallization layers including copper, the so-called inlaid or damascene technique (single and dual) is therefore preferably used wherein a dielectric layer is formed first and then patterned to receive trenches and/or vias, which are subsequently filled with copper or copper alloys.
Another problem in manufacturing a metallization layer is the fact that controversial properties of a single metallization layer within a die region may have to be met with respect to conductivity and minimum pitch between neighboring metal lines. For example, in one region, a high density of metal lines may be present due to a high density of semiconductor devices requiring a large number of electrical connections, while in other die regions, with less critical constraints with respect to a minimum pitch, the resistivity of the metal lines may have to be reduced, thereby requiring, in conventional techniques, increased line widths, which may result in a significantly increased die area occupied by these low-resistivity lines despite the relaxed constraints in view of the line density.
With reference to FIGS. 1a-1b, a typical semiconductor device including a metallization layer will now be described in more detail in order to illustrate conventional approaches and process techniques for forming metal lines in high density areas and low density areas.
FIG. 1a schematically illustrates a semiconductor device 100 comprising a substrate 101, for instance a substrate-on-silicon basis as is frequently used for the formation of integrated circuits and the like. A device layer 102 may be formed above the substrate 101, which may include a plurality of semiconductor devices, such as transistors, capacitors, resistors and the like, depending on the specific circuit layout of a corresponding electronic circuit. For convenience, any such circuit elements are not shown in FIG. 1a. The device layer 102 may define, for instance due to a difference in packing density of circuit elements and the like, a first device region 110A and a second device region 110B, in which is formed a metallization layer 120 which may comprise respective metal lines 121A and 121B, which may be connected to respective conductive regions 130A, 130B by means of corresponding vias 122A, 122B, wherein the regions 130A, 130B may be formed in a dielectric layer 125. Thus, the metal lines 121A, 121B may provide an intra-level electrical connection within the metallization layer 120, while the vias 122A, 122B provide the electrical connection to lower-lying circuit elements and thus finally to the semiconductor devices located in the device layer 102. It should be appreciated that the conductive regions 130A, 130B may represent respective metal lines or metal regions of a lower-lying metallization layer or may represent contact areas of circuit elements. Furthermore, the metallization layer 120 may comprise a dielectric layer 123 formed of any appropriate dielectric material, such as silicon dioxide, silicon oxynitride, silicon nitride, or, in highly advanced applications, the dielectric layer 123 may comprise a low-k dielectric material. It should be appreciated that the term “low-k dielectric material” is to be understood as an insulating material having a relative permittivity of 3.0 or less. Furthermore, an etch stop layer 124 may be provided above the conductive regions 130A, 130B and on top of a corresponding dielectric layer 125, in which the conductive regions 130A, 130B are embedded. It should be appreciated that the metal lines 121A and 121B, which, in sophisticated applications, may comprise copper, may have the same design dimensions, which may be substantially determined by process tolerances of the metal lines 121B formed in the second device region 110B requiring a high line density, for instance due to a required number of electrical connections. In other illustrative embodiments, if the lines 121A in the first device region 110A upon which less critical constraints with respect to a minimum pitch between neighboring metal lines 121A are imposed, the respective line width 121W may be selected greater compared to the lines 121B in order to provide reduced resistivity in the device region 110A, thereby increasing the performance of the metal line 121A in the region 110A. However, a corresponding increase in performance may be obtained at the cost of a significantly increased substrate area, thereby reducing the overall packing density of the semiconductor device 100.
A typical process flow for forming the semiconductor device 100 as shown in FIG. 1a may comprise the following processes. After the formation of any circuit elements in the device layer 102 on the basis of well-established techniques, one or more metallization layers may be formed, wherein the dielectric layer 125 in combination with the conductive regions 130A, 130B may represent one of these metallization layers. In other cases, when the regions 130A, 130B represent conductive areas of circuit elements, appropriate contact technologies may be used. The dielectric layer 125 may be formed on the basis of well-established deposition techniques, such as chemical vapor deposition (CVD) and the like, wherein the conductive regions 130A, 130B may be formed prior to or after the formation of the dielectric layer 125, depending on the specific device level considered. Thereafter, the etch stop layer 124 may be deposited, for instance by plasma enhanced chemical vapor deposition (PECVD) on the basis of well-established techniques, wherein silicon nitride, silicon carbide, nitrogen-enriched silicon carbide and the like, or any combinations thereof, may be used.
Next, in sophisticated techniques, the dielectric layer 123 may be formed by any appropriate process technique, including CVD, spin-on techniques and the like, to provide a desired material composition, such as a low-k dielectric material. Thereafter, depending on process strategies, the vias 122A, 122B may be formed in the dielectric layer 123, for instance by first depositing a portion of the layer 123 and patterning the portion so as to receive respective openings, which may be subsequently filled with an appropriate material, such as a copper-based material including a barrier material, if required. Thereafter, a second portion of the dielectric layer 123 may be deposited and patterned so as to receive respective trenches for forming therein the metal lines 121A, 121B. In other process techniques, the dielectric layer 123 may be deposited with its final thickness and may be patterned to receive trenches first and respective openings for the vias 122A, 122B last, or, in other alternatives, openings for the vias 122A, 122B may be formed first and thereafter trenches for the lines 121A, 121B may be formed subsequently. During the formation of the respective trenches, a respective anisotropic etch process is performed on the basis of well-established recipes, wherein the corresponding etch step is stopped at a desired height within the dielectric layer 123, which is substantially identical for the trenches in the first and second device regions 110A, 110B, except for minor non-uniformities that may be caused by a difference in pattern density and the like.
Thereafter, depending on the process strategy, a barrier material may be formed within the respective trenches, possibly in combination with an appropriate seed layer, and thereafter the metal, such as copper, may be filled in by well-established electrochemical deposition techniques. Any excess material may be removed, for instance by electrochemical polishing, CMP and the like, thereby also planarizing the resulting topography of the metallization layer 120. Due to the patterning process for forming the respective trenches in the first and second device regions 110A, 110B in combination with a common process for filling the trenches, respective process constraints may dictate certain device features, such as a thickness 121T of the metal lines 121B and thus a corresponding thickness of the metal lines 121A, since, due to possible constraints with respect to a high line density in the second device region 110B, the depth of respective trenches and thus the finally obtained thickness 121T may have to be selected so as to provide sufficient process margins for avoiding any short circuits between neighboring metal lines 121B.
FIG. 1b schematically illustrates the device 100 according to another conventional configuration, in which the metallization layer 120 may comprise the dielectric layer 123 in the form of a hybrid structure including an upper portion 123U and a lower portion 123L, which may be comprised of different materials so as to obtain a desired behavior of the dielectric layer 123 in terms of reduced permittivity while nevertheless providing a moderately high mechanical stability. For instance, the upper portion 123U may be comprised of a low-k dielectric material, while the lower portion 123L may be formed of a material having increased mechanical stability compared to the upper portion 123U, such as, for instance, silicon dioxide, fluorine-doped silicon dioxide and the like. However, with respect to the characteristics of the metal lines 121A, 121B, the same criteria apply as previously explained with reference to FIG. 1a. Consequently, when metal lines of different packing density are required in different device regions within a single die area, the conventional technique for the formation of metallization layers may not efficiently allow a combination of low-resistivity metal lines in one region while providing closely spaced metal regions in another die region.
The present disclosure is directed to various methods and systems that may solve, or at least reduce, some or all of the aforementioned problems.